Timing recovery is one of the fundamental operations in digital communications to recover the transmitted data. In general, digital communications can be done in either baseband or passband. In the latter case, the encoded baseband signal is further modulated to a high carrier frequency for transmission. Examples of baseband systems include Fast Ethernet (100 Mb/s) and Gigabit Ethernet over copper (1 Gb/s) as defined by IEEE 802.3ab. Examples of passband communications include gigabit Ethernet over fiber and wireless LAN (local area network) systems as defined by IEEE 802.11a, 11b, and 11g.
In contrast to carrier frequency recovery in passband communications for moving the modulated signal from passband to baseband, timing recovery regenerates a baseband clock for sampling and decoding the baseband signal. Therefore, timing recovery is required in both passband and baseband communications. To achieve proper decoding, timing recovery in the receiver is required to recover the clock of the remote transmitter and to operate at a certain sampling phase to optimize the receiver performance. Various techniques have been devised in the past for timing recovery of remote transmitters. For example, U.S. Pat. Nos. 6,285,726; 6,363,129; 6,577,689; and U.S. patent application 2003/0142687A1 describe applications of timing recovery schemes. The description of the timing recovery systems and the applications in data communication systems of these patent documents are incorporated by reference in their entireties. It is to be understood that the present invention can be implemented in data communication systems with one or more transceivers having receivers and transmitters. Examples of applications of the invention of the present application include IEEE 802.3 Fast Ethernet, Gigabit Ethernet over copper, and ITU-T G.991 high-speed digital-subscriber-line (HDSL) transceiver systems.
Most clock recovery schemes use a phase lock loop (PLL). FIG. 1A illustrates a basic timing recovery scheme involving a phase lock loop 10. As shown in FIG. 1A, the typical phase lock loop 10 consists of a phase detector (PD) 12, a loop filter (LF) 14, and a voltage or current controlled oscillator (VCO or ICO) 16. The purpose of the phase detector 12 is to detect the phase difference between the received signal 18 and the recovered clock signal 20 from the timing recovery mechanism. When the received signal 18 has sufficient transitions and has negligible intersymbol interference (ISI), a simple phase detector 12 that compares the received signal 18 transitions with the voltage or current controlled oscillator output 20 can be deployed. Such schemes have been widely incorporated in timing recovery systems of the past. The purpose of the loop filter 14 is to reduce jitter from a signal 22 from a phase detector 12 to generate a signal 24 whose steady state value can operate the voltage or current controlled oscillator 16 at a frequency equal to that of the received baseband signal.
As also shown in FIG. 1A, once the clock is properly recovered by the phase lock loop 10, it can be fed to an analog-to-digital converter (ADC) 26 to drive the sampling of the received signal 28 in the analog domain and to convert its amplitude to a digital representation 29 for subsequent digital signal processing (DSP) to decode the original transmitted data. In general, the sampling phase of the recovered clock that samples the received signal affects the signal-to-noise ratio (SNR) in digital signal processing DSP, which in turn affects the receiver performance. As illustrated in FIG. 2, the optimum sampling phase of a pulse response is at the “Signal” point. Therefore, it is important for the timing recovery system to regenerate a clock that is optimum in phase to sample the received analog signal.
Although many timing recovery designs have the same general phase lock loop structure shown in FIG. 1A, actual implementation of the phase detector PD, loop filter LF, and voltage VCO or current controlled oscillator ICO can be very different for different applications. As illustrated in FIG. 1B, one method of phase detection is by a method commonly called edge detection. In this detection scheme, the phase difference 35 is simply determined by measuring the lag from the leading edge 32 of a received data 34 pulse to the leading edge 36 of a recovered clock 38 pulse that is immediately after the data pulse. However, as illustrated in FIG. 2, when the received signal 41 suffers from a strong intersymbol interference (ISI) due to a band limited channel, a simple edge detection phase detector PD will fail, as the received signal has rising and falling slopes corresponding to precursor intersymbol interference ISI 42 and postcursor intersymbol interference ISI 44 and therefore has no clear step transitions like those of square pulses, and therefore no clear leading edges. One way to deal with this problem is to correlate the received signal with the detected output. From statistics, one can show that the correlation output between the two signals is a monotonic function of the phase difference between the data transitions and the recovered clock. The correlation, thus, can be used in the phase detector PD to generate the phase error term. This approach, known in the prior art, is commonly referred as the Mueller-Muller (M&M) method and is illustrated in FIG. 3. In FIG. 3, the received signal 45 (having value rk) and the detected signal (e.g., the slicer output) 43 (having value ak) are used for a computation by the M&M method for phase detection given as follows.zk=rk−1ak−ak−1rkFour DFF's (digital flip-flop) 46 in FIG. 3 are used to generate the delay versions of the received signal 45 and detected signal 43. The computation output (zk) is sent to a loop filter (LF) 49 to drive VCO(or ICO) 48, which can be either voltage or current controlled oscillator. For those who are skilled in the art, the above equation can be modified according to the statistics of the decoded output ak and the pulse respones shown in FIG. 2 so that the computation output (zk) can generate a similar phase error term.
One critical limitation of the Mueller-Muller M&M method, however, is that it requires correct detection of the original transmitted symbols (ak), which in turn requires proper equalization adaptation to reduce the intersymbol interference ISI for correction detection. To remove or reduce intersymbol interference ISI for correct signal detection, a typical receiver 50, as shown in FIG. 4, includes both the feed-forward-equalizer (FFE) 52 and decision-feedback-equalizer (DFE) 54. A received (or incoming) signal 51 with ISI is processed by the receiver 50. As used herein, the term “strong intersymbol interference ISI” refers to intersymbol interference ISI that needs equalization adaptation for signal detection. The result of this equalization is fed to a slicer 56, which detects the original transmitted amplitude from the input signal level. Since the channel impulse is unknown, both equalizers 52, 54 need to be trained to more efficiently remove or reduce the ISI. A standard method of training the equalizer is called stochastic least-mean-square (LMS) method. In brief, this method computes the difference between the slicer 56 input and output, called Slicer Error, and uses this error output to adapt the equalizer coefficients. The decoded slicer output 58 is fed to the Mueller-Muller (M&M) phase detector PD 57, whose output is in turn fed to a loop filter 61, and passes to a voltage VCO (or current controlled oscillator ICO) 62. This stochastic least-mean-square LMS training method, however, does not always work. One condition for the stochastic least-mean-square LMS method to be successful in training the equalizer is to sample the received signal at a good phase, which needs to be within a certain range.
When intersymbol interference ISI is strong and before the equalizer is properly trained, the decoded output may have many errors. As a result, the decoded output 58 fed to the Mueller-Muller M&M phase detector PD 57 would not generate a correct phase error for clock recovery. Since successful equalizer training depends on good clock recovery, the challenge for proper timing recovery and equalizer training becomes a “chicken-and-egg” problem, i.e., one needs good clock recovery to train the equalizer, but one also needs a trained equalizer to recover the clock.
Another limitation of the Mueller-Muller (M&M) method is that it does not provide information related to optimum phase sampling for maximizing the signal detection performance. Although, as shown in FIG. 4, the M&M phase detector PD 57 generates an output that is a monotonic function of the phase error, its zero crossing does not necessarily correspond to the optimum phase that results in the maximum signal to noise ratio SNR in digital signal processing DSP. In fact, the zero-crossing location is dependent on the channel impulse response.
To solve the timing recovery problem in the presence of strong intersymbol interference ISI, several different schemes have been proposed. In one method, a pre-cursor filter is introduced between the analog-to-digital converter ADC 60 output and the feed forward equalizer FFE 52 input to shape the received waveform for Mueller-Muller M&M based timing recovery. In another method, a separate clock that runs at 8/7 of the symbol clock is used to present the timing recovery problem to an interpolation problem of analog-to-digital converter ADC output samples. In both of these prior methods, the decoded output 58 from the slicer 56 is still used to control the timing. Therefore, they are still subject to the mutual dependence issue of the equalizer training and timing recovery.
In yet another method of timing recovery, a separate analog-to-digital converter ADC 70 (not the one shown in FIG. 1 for signal detection) that operates at twice (2 times) of the symbol rate (or baud rate) is used (referred as 2×ADC). Symbol rate is the number of symbols per second transmitted, where each symbol is a modulated pulse that carries a certain number of information bits. For example, in the case of 10 Mb/s Ethernet, the symbol rate is 10 M (mega) symbols per second, and each symbol carries one bit. The data rate is 10 Mb/s. For gigabit Ethernet, the symbol rate is 125 MHz, and each symbol is a vector of four signals. That is, four parallel lines are transmitted inside a CAT-5 Ethernet cable. Each four-vector symbol together carries 8 information bits. Therefore, the total data rate is 1 gigabit per second. In telecommunication terminology, symbol rate and baud rate are used interchangeably. That is, they mean exactly the same thing. On the other and, symbol rate and data rate are different. The relationship can be represented by: (data rate)=(symbol rate)×(net information bit carried by each symbol). This method of timing recovery samples the received analog signal 72 to generate two sample streams with their sampling phase difference by half of the symbol interval, as shown in FIG. 5. In this method, the received analog signal 72 is converted to digital signal by the 2×ADC 70 and is processed by the demultiplexer 74 into an even stream 76 and an odd stream 78. A 2×ADC uses a sampling clock that is twice of the symbol rate to sample the received signal stream and to convert the analog signal to digital signal, whereas a 1×ADC uses a sampling clock that is at the same symbol rate to sample a received signal stream at the symbol rate to convert the signal from analog to digital format. As a result, a 2×ADC generates two samples from the received analog signal every symbol interval, and a 1×ADC generates only one sample every symbol interval. An even sample stream of a 2×ADC is a sample stream from every other sample of the 2×ADC output, and an odd sample stream of the 2×ADC is a sample stream of samples that interleave with the even sample stream. Therefore, the even and odd sample streams have a sampling time difference of half of the symbol interval, and both the even sample stream and the odd sample stream have one sample every symbol interval. With these two streams of samples, as shown in FIG. 5A, autocorrelations R[0] and R[1] for each of these streams are computed by calculator processor 80, 82 to generate a phase error output 84 for driving the loop filter (LF) 86. Output from the loop filter 86 is passed to a voltage or current controlled oscillator VCO 88, the output of which goes back to the 2×ADC 70 for feedback. This method does not require input from either the equalizer output or the slicer output. Therefore, it avoids the need to have a correct detected output and can robustly recover the clock. Once the clock is recovered, a delayed version of the clock that maximizes R[0]−R[1] can be used to sample the received signal for DSP.
FIG. 5B illustrates a receiver 90 that incorporates the timing recovery scheme of FIG. 5A. A separate 1×ADC analog to digital converter is used to sample the received signal for equalizer training and signal detection. An incoming analog signal 72 passes to the timing recovery system 92 according to the timing recovery scheme of FIG. 5A. A clock signal 94 is recovered from the incoming signal and is delayed through a delay-tap logic (which includes delay select logic 96 and delay taps 98) for driving the sampling the 1×ADC analog to digital converter 100 to convert the incoming analog signal 72. The digital output from the 1×ADC 100 is sent through the equalizer 102 to the detector 104 to result in recovered data 106. To train the equalizer, the output from the 1×ADC 100 is processed through processor 108 to find the difference in autocorrelations R[0]−R[1] to determine the additional delay for the sampling clock 99 via the delay logic.
The method of FIG. 5A and FIG. 5B, however, still has limitations. First, it requires a separate ADC, i.e., it needs to have two ADC's (analog to digital converters) for processing one received signal stream—one 2×ADC to recover the clock and another 1×ADC to train the equalizers. The reason is that the sampling phase from the clock recovery is not within the range for the equalizer to be trained. Therefore, a separate 1×ADC is required for actual signal detection, and its sampling clock has a certain delay from that of the recovered clock. The second limitation is that the 2×ADC used in clock recovery operates at twice of the symbol rate (i.e., a 2×ADC is needed). This thus requires higher speed implementation.
Thus, there is a need for a clock recovery technique and system in which less demanding analog to digital converter systems are required.